An analog-to-digital converter (ADC) configured to convert an analog signal to digital bits. The ADC includes a plurality of sub-ADCs that are cascaded in a pipeline. Each sub-ADC may be configured to sample an input signal that is fed to each sub-ADC and convert the sampled input signal to a pre-configured number of digital bits. Each sub-ADC except a last sub-ADC in the pipeline is configured to generate a residue signal and feed the residue signal as the input signal to a succeeding sub-ADC in the pipeline. At least one sub-ADC is configured to determine a most-significant bit (MSB) of the pre-configured number of digital bits while the input signal is sampled. The ADC may include a plurality of residue amplifiers for amplifying a residue signal. The sub-ADCs may be successive approximation register (SAR) ADCs or flash ADCs.