Invention Grant
- Patent Title: Methods of aligning a semiconductor wafer for singulation
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Application No.: US17068129Application Date: 2020-10-12
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Publication No.: US11289381B2Publication Date: 2022-03-29
- Inventor: Michael J. Seddon , Takashi Noma
- Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Applicant Address: US AZ Phoenix
- Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee Address: US AZ Phoenix
- Agency: Adam R. Stephenson, Ltd.
- Main IPC: H01L21/78
- IPC: H01L21/78 ; H01L21/66 ; H01L21/3205 ; H01L21/683 ; H01L21/02 ; H01L21/304
Abstract:
Implementations of a method for aligning a semiconductor wafer for singulation may include: providing a semiconductor wafer having a first side and a second side. The first side of the wafer may include a plurality of die and the plurality of die may be separated by streets. The semiconductor wafer may include an edge ring around a perimeter of the wafer on the second side of the wafer. The wafer may also include a metal layer on the second side of the wafer. The metal layer may substantially cover the edge ring. The method may include grinding the edge ring to create an edge exclusion area and aligning the semiconductor wafer with a saw using a camera positioned in the edge exclusion area on the second side of the wafer. Aligning the wafer may include using three or more alignment features included in the edge exclusion area.
Public/Granted literature
- US20210028064A1 METHODS OF ALIGNING A SEMICONDUCTOR WAFER FOR SINGULATION Public/Granted day:2021-01-28
Information query
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