Invention Grant
- Patent Title: Integration method of ferroelectric memory array
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Application No.: US16729273Application Date: 2019-12-27
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Publication No.: US11289497B2Publication Date: 2022-03-29
- Inventor: Gaurav Thareja , Sasikanth Manipatruni , Rajeev Kumar Dokania , Ramamoorthy Ramesh , Amrita Mathuriya
- Applicant: Kepler Computing, Inc.
- Applicant Address: US CA San Francisco
- Assignee: Kepler Computing, Inc.
- Current Assignee: Kepler Computing, Inc.
- Current Assignee Address: US CA San Francisco
- Agency: Mughal IP P.C.
- Main IPC: H01L27/11507
- IPC: H01L27/11507 ; H01L49/02 ; G11C11/22
Abstract:
Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.
Public/Granted literature
- US20210202510A1 INTEGRATION METHOD OF FERROELECTRIC MEMORY ARRAY Public/Granted day:2021-07-01
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