Invention Grant
- Patent Title: Method of and an arrangement for analyzing manufacturing defects of multi-chip modules made without known good die
-
Application No.: US17076496Application Date: 2020-10-21
-
Publication No.: US11293979B2Publication Date: 2022-04-05
- Inventor: Peter Shun Shen Wang
- Applicant: Peter Shun Shen Wang
- Applicant Address: US NJ Gillette
- Assignee: Peter Shun Shen Wang
- Current Assignee: Peter Shun Shen Wang
- Current Assignee Address: US NJ Gillette
- Agent Chi Eng
- Main IPC: G01R31/3177
- IPC: G01R31/3177 ; G01R31/317 ; G01R31/3183 ; G01R31/3185 ; G01R31/28

Abstract:
The present invention provides a reliable method and arrangement for boundary scan testing and debugging newly manufactured multi-chip modules (MCMs) made to identical design specifications with no Known Good Die therein. Advantageously, a first and a second MCM are temporarily linked in tandem for boundary scan testing through a motherboard and daisy-chaining their internal dice, and interlinking the corresponding boundary scan cells of the identical dice of the first and second MCM to (1) run self-test on individual MCMs and mutual test on the MCMs connected in tandem in order to generate an extended Truth Table that includes responses from an array of combined netlists of the first and second MCMs, and (2) to diagnose mismatched bits in the extended Truth Table using a Boundary Scan Diagnostics software so as to identify defects in the first and second MCMs.
Public/Granted literature
Information query