Invention Grant
- Patent Title: Customer-transparent logic redundancy for improved yield
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Application No.: US17132820Application Date: 2020-12-23
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Publication No.: US11293980B2Publication Date: 2022-04-05
- Inventor: Igor Arsovski , John R. Goss , Eric D. Hunt-Schroeder , Andrew K. Killorin
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Roberts Calderon Safran & Cole, P.C.
- Agent L. Jeffrey Kelly; Andrew M. Calderon
- Main IPC: G01R31/3177
- IPC: G01R31/3177

Abstract:
Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.
Public/Granted literature
- US20210116498A1 CUSTOMER-TRANSPARENT LOGIC REDUNDANCY FOR IMPROVED YIELD Public/Granted day:2021-04-22
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