A memory controller capable of detecting a code having an error among codes stored in a Read Only Memory (ROM) controls a memory device. The memory controller includes: a code memory for storing codes used to perform an operation; a code executor for executing the codes stored in the code memory to perform the operation; a debug controller for setting a suspend code address for suspending the execution of the codes used to perform the operation; an initialization controller for controlling an initialization operation of at least one of the debug controller and the code executor; and an interfacing component for receiving a suspend code setting request corresponding to an operation of setting the suspend code address and providing the received suspend code setting request to the debug controller.