A delay adjustment circuit, comprising: a detection circuit configured to output a control signal upon detecting a data signal edge; a timing circuit configured to obtain a setup time and a hold time according to the control signal; a computation circuit configured to perform a computation with respect to a plurality of setup times and a plurality of hold times so as to obtain time information of a row data signal; and an adjustment circuit configured to correspondingly adjust, according to the time information and a preset relative time delay, a relative time delay between an output data signal and a clock signal.