According to one embodiment, a memory system includes a plurality of memory packages, on-die termination (ODT) circuits, and a controller. The plurality of memory packages are coupled by a common bus and arranged in groups, each group includes a pair of memory packages facing each other, and each memory package includes a plurality of memory chips. The ODT circuits are respectively disposed in the memory packages. The ODT circuits are on/off controlled based on an asserted state of a chip enable signal CEn acquired using a periodic signal of at least two cycles.