A controller utilizes dual sense bin balancing (DSBB) to adjust a read level between memory states of an array of NAND flash memory cells. One or more iterations of DSBB may be performed to provide a read level. Each iteration of the DSBB includes performing a first sense read, performing a second sense read, determining a read error, and adjusting the initial read level. The first sense read is performed at a first offset of an initial read level of memory cells. The second sense read is performed at a second offset of the initial read level of memory cells. A read error is determined from the first sense read and the second sense read. The read level is adjusted by the read error. A read of the randomized data pattern is conducted with the adjusted read level of a last iteration of the DSBB.