Invention Grant
- Patent Title: Multi-layer barrier for CMOS under array type memory device and method of making thereof
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Application No.: US16860358Application Date: 2020-04-28
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Publication No.: US11296112B2Publication Date: 2022-04-05
- Inventor: Fumitaka Amano
- Applicant: SANDISK TECHNOLOGIES LLC
- Applicant Address: US TX Addison
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Addison
- Agency: The Marbury Law Group PLLC
- Main IPC: H01L27/11582
- IPC: H01L27/11582 ; H01L27/11556 ; H01L29/167 ; H01L27/11573 ; H01L27/11526 ; H01L27/11521 ; H01L27/11568 ; H01L21/768 ; H01L21/265 ; H01L23/485 ; H01L29/45 ; H01L23/532
Abstract:
A semiconductor structure includes a doped semiconductor material portion, a metal-semiconductor alloy portion contacting the doped semiconductor material portion, a device contact via structure in direct contact with the metal-semiconductor alloy portion, and at least one dielectric material layer laterally surrounding the device contact via structure. The device contact via structure includes a barrier stack and a conductive fill material portion. The barrier stack includes at least two metal nitride layers and at least one nitrogen-containing material layer containing nitrogen and an element selected from silicon or boron.
Public/Granted literature
- US20200258909A1 MULTI-LAYER BARRIER FOR CMOS UNDER ARRAY TYPE MEMORY DEVICE AND METHOD OF MAKING THEREOF Public/Granted day:2020-08-13
Information query
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