A clock device includes a first phase interpolator circuit, a detector circuit, and a digital controller circuitry. The first phase interpolator circuit generates a second reference clock signal according to a first control signal and at least one first reference clock signal. The detector circuit generates an error signal according to a difference between a receiver signal and the second reference clock signal, in which the receiver signal is a receiver clock signal from a receiver circuit or an input signal that has been equalized by the receiver circuit. The digital controller circuitry generates the first control signal and a second control signal according to the error signal, and updates the second control signal according to a change of the first control signal, in which the second control signal is for generating a transmitter clock signal of a transmitter circuit.