Invention Grant
- Patent Title: Ordered sets for high-speed interconnects
-
Application No.: US16723868Application Date: 2019-12-20
-
Publication No.: US11296994B2Publication Date: 2022-04-05
- Inventor: Debendra Das Sharma
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: H04L12/801
- IPC: H04L12/801 ; H04L12/12 ; H04L1/20 ; H04L47/34

Abstract:
A system and apparatus can include a port for transmitting data; and a link coupled to the port. The port can include a physical layer device (PHY) to decode a physical layer packet, the physical layer packet received across the link. The physical layer packet can include a first bit sequence corresponding to a first ordered set, and a second bit sequence corresponding to a second ordered set, the first bit sequence immediately adjacent to the second bit sequence. The first ordered set is received at a predetermined ordered set interval, which can occur following a flow control unit (flit). The first ordered set comprises eight bytes and the second ordered set comprises eight bytes. In embodiments, bit errors in the ordered sets can be determined by checking bits received against expected bits for the ordered set interval.
Information query