Implementing an application using a plurality of data processing engines (DPEs) can include, in a first pass, mapping, using computer hardware, a data flow graph onto an array of DPEs by minimizing direct memory access (DMA) circuit usage and memory conflicts in the array of DPEs and, in response to determining that a mapping solution generated by the first pass requires an additional DMA circuit not specified by the data flow graph, inserting, using the computer hardware, additional buffers into the data flow graph. In a second pass, the additional buffers can be mapped, using the computer hardware, onto the array of DPEs by minimizing the memory conflicts in the array of DPEs.