Invention Grant
- Patent Title: Memory system configured with a synthesized logical block into which a plurality of data units forming an error correction frame are written
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Application No.: US16704555Application Date: 2019-12-05
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Publication No.: US11301387B2Publication Date: 2022-04-12
- Inventor: Hirokazu Takeuchi , Takahiro Miomo , Hiroyuki Yamaguchi , Hajime Yamazaki
- Applicant: KIOXIA Corporation
- Applicant Address: JP Tokyo
- Assignee: KIOXIA Corporation
- Current Assignee: KIOXIA Corporation
- Current Assignee Address: JP Tokyo
- Agency: Kim & Stewart LLP
- Priority: JPJP2017-059072 20170324
- Main IPC: G11C29/52
- IPC: G11C29/52 ; G06F12/0862 ; G06F11/10 ; G06F12/10 ; G11C29/00 ; G06F12/06 ; G06F12/0868 ; H03M13/15 ; G11C29/04 ; G11C29/44 ; H03M13/27

Abstract:
A memory system includes a memory and a memory controller. The memory includes first and second parallel operation elements, each including a plurality of first and second storage regions, respectively, and first and second buffers, respectively. The memory controller performs operations on the memory based on first and second group information. The first group information defines first groups, each first group including one first storage region and one second storage region, and each second group including at least two first groups. The memory controller, in response to a host command targeting a first storage region, (i) acquires first data from the first buffer, and thereafter (ii) causes the memory to read out second data to the first buffer. The first storage region storing the first data and the second storage region storing the second data belong to different first groups and to the same second group.
Information query