A memory device includes a memory bank having a set of word lines, a bank control block coupled to the memory bank, wherein the bank control block when in operation provides timing control and data control to facilitate execution of commands to and from the memory bank and a command decoder coupled to the bank control block. The command decoder when in operation transmits to the bank control block a refresh (REF) command associated with a first pump to refresh a memory cell of the memory bank and a row hammer refresh (RHR) command associated with a second pump to refresh a second memory cell of the memory bank in conjunction with a refresh operation, and the bank control block when in operation transmits a first control signal to the command decoder to determine which automatic error check and scrub (AECS) mode operation is selected.