Invention Grant
- Patent Title: Compact and efficient CMOS inverter
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Application No.: US16836590Application Date: 2020-03-31
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Publication No.: US11302586B2Publication Date: 2022-04-12
- Inventor: Amitay Levi , Dafna Beery , Andrew J. Walker
- Applicant: Integrated Silicon Solution, (Cayman) Inc.
- Applicant Address: KY Grand Cayman
- Assignee: Integrated Silicon Solution, (Cayman) Inc.
- Current Assignee: Integrated Silicon Solution, (Cayman) Inc.
- Current Assignee Address: KY Grand Cayman
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L27/092 ; H01L23/535 ; H01L29/78 ; H01L21/02 ; H01L21/3065 ; H01L21/308 ; H01L29/66
Abstract:
A structure for providing an inverter circuit employing two vertical transistor structures formed on a semiconductor substrate. The vertical semiconductor structures each include a semiconductor pillar structure and a surrounding gate dielectric. A gate structure is formed to at least partially surround the first and second vertical transistor structures. The semiconductor substrate is formed into first and section regions that are separated by a dielectric isolation structure. The first region includes a P+ doped portion and an N+ doped portion, and the second region includes an N+ doped portion and a P+ doped portion. The N+ and P+ doped portions of the first and second regions can be arranged such that the N+ doped portion of the first region is adjacent to the P+ doped portion of the second region, and the P+ doped portion of the first region is adjacent to the N+ doped portion of the second region.
Public/Granted literature
- US20210305105A1 COMPACT AND EFFICIENT CMOS INVERTER Public/Granted day:2021-09-30
Information query
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