A fuse latch of a semiconductor device is disclosed. The fuse latch of the semiconductor device includes a plurality of PMOS transistors and a plurality of NMOS transistors. The fuse latch includes PMOS transistors and NMOS transistors configured to latch fuse cell data. In the fuse latch, the plurality of PMOS transistors and the plurality of NMOS transistors are arranged in a shape of two lines in each active region in a second direction.