Invention Grant
- Patent Title: Partitioning in post-layout circuit simulation
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Application No.: US16046957Application Date: 2018-07-26
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Publication No.: US11308253B2Publication Date: 2022-04-19
- Inventor: Ningjia Zhu
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Fenwick & West LLP
- Main IPC: G06F30/392
- IPC: G06F30/392 ; G06F30/327 ; G06F111/04 ; G06F111/20 ; G06F119/06

Abstract:
The independent claims of this patent signify a concise description of embodiments. New techniques for the partitioning of big element blocks in a circuit are disclosed. The techniques partition both pre-layout and post-layout circuits. If a post-layout circuit has different simulation results from a pre-layout circuit, the techniques determine where and how “cross-talk” of the RC networks due to RC extraction is changing the circuit physics behavior from the original design of the circuit. A flow of the local circuit simulation of the pre-layout netlist and the post-layout netlist of the same design is presented. A flow of reference or relative or differential circuit simulation of a known design and a new design of the same kind is described. This Abstract is not intended to limit the scope of the claims.
Public/Granted literature
- US20190034574A1 PARTITIONING IN POST-LAYOUT CIRCUIT SIMULATION Public/Granted day:2019-01-31
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