Embodiments relate to a signal detector circuit suitable for a display device that detects and decodes a power line communication signal. The signal detector circuit includes an averaging circuit, a comparator, a sampling circuit, a decoder circuit, and a regulator circuit. The averaging circuit receives the power line communication signal and averages the power line communication signal over time to generate an average signal. The comparator compares the average signal to the power line communication signal and generates a comparison signal. The sampling circuit samples the comparison signal according to a sample timing of a clock signal and generates a sampled signal. The decoder circuit decodes the sampled signal and generates a decoded output signal. The regulator circuit receives the power line communication signal and generates supply voltage to power the comparator, the sampling circuit, and the decoder circuit.