Invention Grant
- Patent Title: Semiconductor circuit and semiconductor circuit system to suppress disturbance in the semiconductor circuit
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Application No.: US16768880Application Date: 2018-11-29
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Publication No.: US11309025B2Publication Date: 2022-04-19
- Inventor: Yusuke Shuto
- Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
- Applicant Address: JP Kanagawa
- Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
- Current Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
- Current Assignee Address: JP Kanagawa
- Agency: Chip Law Group
- Priority: JPJP2017-237980 20171212
- International Application: PCT/JP2018/044033 WO 20181129
- International Announcement: WO2019/116915 WO 20190620
- Main IPC: G11C14/00
- IPC: G11C14/00

Abstract:
A semiconductor circuit includes a first circuit that applies an inverted voltage of a voltage at a first node to a second node, a second circuit that applies an inverted voltage of a voltage at the second node to the first node, a first transistor that couples the first node to a third node, and a first memory element having a first terminal coupled to the third node and a second terminal to which a control voltage is to be applied. The semiconductor circuit further includes a second transistor having a drain coupled to the third node and a gate coupled to one of the first node or the second node, a third transistor having a drain coupled to the third node and a gate coupled to the other of the first node or the second node, and a driver.
Public/Granted literature
- US20210166760A1 SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR CIRCUIT SYSTEM Public/Granted day:2021-06-03
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