Apparatuses and techniques for detecting short circuits in a memory device, and in particular, word line-to-channel short circuits and short circuits between bit line contacts at the top of NAND strings. A short circuit detection operation includes a channel pre-clean phase which discharges a channel of a non-short circuited NAND string while boosting a bit line of a short circuited NAND string, followed by a bit line pre-charge phase which boosts a bit line of the non-short circuited NAND string, followed by a bit line discharge phase which discharges the bit line of the non-short circuited NAND string, followed by a sensing phase which identifies the short circuited NAND strings as being in a programmed or non-conductive state.