Invention Grant
- Patent Title: Semiconductor structure and method for forming the same
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Application No.: US16818051Application Date: 2020-03-13
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Publication No.: US11309182B2Publication Date: 2022-04-19
- Inventor: Zhao Junhong , Zhao Hai
- Applicant: Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
- Applicant Address: CN Shanghai; CN Beijing
- Assignee: Semiconductor Manufacturing International (Shanghai) Corporation,Semiconductor Manufacturing International (Beijing) Corporation
- Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation,Semiconductor Manufacturing International (Beijing) Corporation
- Current Assignee Address: CN Shanghai; CN Beijing
- Agency: Crowell & Moring LLP
- Priority: CN201910702059.8 20190731
- Main IPC: H01L21/033
- IPC: H01L21/033

Abstract:
A semiconductor structure and a method for forming the same are provided. In one form, the method includes: providing a base, where a bottom core material layer is formed on the base, a plurality of discrete top core layers is formed on the bottom core material layer, an area between top core layers of the plurality of adjacent top core layers is a groove, and the groove includes a connecting groove; forming a first spacer film conformally covering the plurality of discrete top core layers and the bottom core material layer; forming a blocking structure in a remainder of the connecting groove exposed from the first spacer film; removing first spacer films on a top of the top core layers of the plurality of discrete top core layers and on the bottom core material layer using the blocking structure as a mask, to form a first mask spacer; removing the plurality of top core layers; patterning the bottom core material layer using the first mask spacer and the blocking structure as a mask, to form a bottom core layer; forming a second mask spacer on a side wall of the bottom core layer; and removing the bottom core layer. Through the blocking structure, a bottom core layer at a position corresponding to the connecting groove has a relatively large width, thereby directly forming target patterns with different spacings.
Public/Granted literature
- US20210035803A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME Public/Granted day:2021-02-04
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