Invention Grant
- Patent Title: Overlapping die stacks for NAND package architecture
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Application No.: US17003789Application Date: 2020-08-26
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Publication No.: US11309281B2Publication Date: 2022-04-19
- Inventor: Enyong Tai , Hem P. Takiar , Li Wang , Hong Wan Ng
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/00 ; H01L25/18 ; H01L25/00

Abstract:
A semiconductor device assembly includes a substrate having a plurality of external connections, a first stack of semiconductor dies disposed directly over a first location on the substrate and electrically coupled to a first subset of the plurality of external connections, and a second stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. A portion of the semiconductor dies of the second stack overlaps a portion of the semiconductor dies of the first stack. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first stack and the second stack.
Public/Granted literature
- US20220068877A1 OVERLAPPING DIE STACKS FOR NAND PACKAGE ARCHITECTURE Public/Granted day:2022-03-03
Information query
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