Invention Grant
- Patent Title: Methods of resistance and capacitance reduction to circuit output nodes
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Application No.: US16787964Application Date: 2020-02-11
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Publication No.: US11309311B2Publication Date: 2022-04-19
- Inventor: Po-Chia Lai , Shang-Wei Fang , Meng-Hung Shen , Jiann-Tyng Tzeng , Ting-Wei Chiang , Jung-Chan Yang , Stefan Rusu
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L29/40 ; H01L27/07 ; H01L27/02 ; H01L23/485 ; G06F30/392 ; H01L23/64 ; G06F30/394

Abstract:
An integrated circuit is disclosed, including a first conductive pattern and a second conductive pattern that are disposed in a first layer and extend in a first direction, at least one first conductive segment disposed in a second layer different from the first layer, and at least one via disposed between the first layer and the second layer. The at least one via is coupled between the at least one first conductive segment and one or both of the first conductive pattern and the second conductive pattern, at an output node of the integrated circuit. The at least one via comprises a tapered shape with a width that decreases from a first width to a second width narrower than the first width. The first width of the at least one via is greater than widths of the first conductive pattern and the second conductive pattern.
Public/Granted literature
- US20210249407A1 METHODS OF RESISTANCE AND CAPACITANCE REDUCTION TO CIRCUIT OUTPUT NODES Public/Granted day:2021-08-12
Information query
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