Invention Grant
- Patent Title: Method of manufacturing an LDMOS device having a well region below a groove
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Application No.: US16770362Application Date: 2018-12-05
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Publication No.: US11309406B2Publication Date: 2022-04-19
- Inventor: Nailong He , Sen Zhang , Guangsheng Zhang , Yun Lan
- Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
- Applicant Address: CN Jiangsu
- Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
- Current Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
- Current Assignee Address: CN Jiangsu
- Agency: Polsinelli PC
- Priority: CN201711278066.7 20171206
- International Application: PCT/CN2018/119252 WO 20181205
- International Announcement: WO2019/109924 WO 20190613
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/762 ; H01L29/417 ; H01L21/033 ; H01L29/06 ; H01L29/78 ; H01L29/423

Abstract:
A manufacturing method of an LDMOS device comprises: obtaining a wafer formed with a doped region having a first conductivity type, wherein a top buried layer is formed inside the doped region having the first conductivity type, and a field oxide insulation layer structure is formed on the top buried layer; disposing a trench on the doped region having the first conductivity type, wherein the trench extends to the top buried layer and the field oxide insulation layer structure such that a portion of the top buried layer is removed; injecting an ion of a second conductivity type to form a well region below the trench; and forming a doped source region in the well region. The first conductivity type and the second conductivity type are opposite conductivity types.
Public/Granted literature
- US20210175347A1 LDMOS DEVICE AND MANUFACTURING METHOD THEREOF Public/Granted day:2021-06-10
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