An arithmetic processing device includes an arithmetic circuit and a memory access controller performing access control for a read request on a memory module including a volatile memory and a nonvolatile memory, the volatile memory operating as a cache of the nonvolatile memory. The memory access controller stores an address table on which unit addresses including a request address of the read request are registered, issues a speculative read to the memory module in response to the read request and update the address table when the request address is included in the unit addresses in the address table, and issues a normal read when the request address is not included in any of the unit addresses. When the normal read is issued, read data is received after transmitting a transmission request signal. When the speculative read is issued, read data are acquired when receiving a hit flag.