Various implementations described herein are directed to a device having memory with a first array and a second array. The device may have power rails formed in frontside metal layers that supply core voltage to the memory. The power rails may include a first path routed through a first frontside metal layer to the first array of the memory, and the power rails may include a second path routed through the first frontside metal layer and a second frontside metal layer to the second array of the memory.