Invention Grant
- Patent Title: Low power memory state retention regulator
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Application No.: US17030134Application Date: 2020-09-23
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Publication No.: US11315655B2Publication Date: 2022-04-26
- Inventor: Nidhi Chaudhry , Dale John McQuirk , Miten H. Nagda
- Applicant: NXP USA, Inc.
- Applicant Address: US TX Austin
- Assignee: NXP USA, Inc.
- Current Assignee: NXP USA, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: G11C29/44
- IPC: G11C29/44 ; G11C7/10 ; G11C29/12 ; G11C29/02 ; G11C7/14

Abstract:
A regulator includes an error amplifier with a first input coupled to receive a reference voltage and a second input coupled to receive a feedback signal. A driver transistor provides an output voltage of the regulator that powers a memory. A replica transistor provides a replica voltage that powers a replica of the memory. A first ratio of a size of the replica of the memory to a size of the memory is less than one, and a second ratio of a drive strength of the replica transistor to a drive strength of the driver transistor is less than one. Each of the first ratio and the second ratio is at most 1/500. Switching circuitry provides one of the output voltage or the replica voltage as the feedback signal to the error amplifier.
Public/Granted literature
- US20220093204A1 LOW POWER MEMORY STATE RETENTION REGULATOR Public/Granted day:2022-03-24
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