Invention Grant
- Patent Title: LDMOS transistors including vertical gates with multiple dielectric sections, and associated methods
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Application No.: US15997997Application Date: 2018-06-05
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Publication No.: US11316044B2Publication Date: 2022-04-26
- Inventor: Tom K. Castro , Rajwinder Singh , Badredin Fatemizadeh , Adam Brand , John Xia , Chi-Nung Ni , Marco A. Zuniga
- Applicant: Maxim Integrated Products, Inc.
- Applicant Address: US CA San Jose
- Assignee: Maxim Integrated Products, Inc.
- Current Assignee: Maxim Integrated Products, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Lathrop GPM LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/06 ; H01L29/417 ; H01L29/423 ; H01L29/66 ; H01L29/40 ; H01L27/092 ; H01L21/8238

Abstract:
A lateral double-diffused metal-oxide-semiconductor transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate include a (a) gate conductor extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure and (b) a gate dielectric layer including a least three dielectric sections. Each of the at least three dielectric sections separates the gate conductor from the silicon semiconductor structure by a respective separation distance, where each of the respective separation distances is different from each other of the respective separation distances.
Public/Granted literature
- US20180350980A1 LDMOS TRANSISTORS INCLUDING VERTICAL GATES WITH MULTIPLE DIELECTRIC SECTIONS, AND ASSOCIATED METHODS Public/Granted day:2018-12-06
Information query
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