Invention Grant
- Patent Title: Method, device, and computer program for improving synchronization of clocks in devices linked according to a daisy-chain topology
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Application No.: US16465518Application Date: 2017-12-04
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Publication No.: US11316605B2Publication Date: 2022-04-26
- Inventor: Romain Guignard , Yacine El Kolli , Lionel Le Scolan , Arnaud Closset
- Applicant: CANON KABUSHIKI KAISHA
- Applicant Address: JP Tokyo
- Assignee: CANON KABUSHIKI KAISHA
- Current Assignee: CANON KABUSHIKI KAISHA
- Current Assignee Address: JP Tokyo
- Agency: Canon U.S.A., Inc. IP Division
- Priority: GB1620718 20161206
- International Application: PCT/EP2017/081389 WO 20171204
- International Announcement: WO2018/104237 WO 20180614
- Main IPC: H04J3/06
- IPC: H04J3/06

Abstract:
A method for synchronizing a logical clock in a device comprising a physical clock, an input port, and an output port, the device further comprising a logical clock and a time compensation clock sharing the physical clock, the time compensation clock making it possible to determine a residence time, comprising obtaining a theoretical residence time, during a pre-synchronization phase according to which the logical clock is not synchronized, adding a value representative of the obtained theoretical residence time to a residence time value stored in a synchronization message to be forwarded, during a synchronization phase according to which the logical clock is synchronized, obtaining a residence time and adding a value representative of the obtained residence time to a residence time value stored in a synchronization message to be forwarded, and synchronizing the logical clock as a function of a residence time value stored in a received synchronization message.
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