Invention Grant
- Patent Title: Secure scan entry
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Application No.: US16801447Application Date: 2020-02-26
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Publication No.: US11320482B2Publication Date: 2022-05-03
- Inventor: Mudit Srivastava , Raghavendra Pai Kateel , HengWee Cheng , Anil Shirwaikar
- Applicant: Silicon Laboratories Inc.
- Applicant Address: US TX Austin
- Assignee: Silicon Laboratories Inc.
- Current Assignee: Silicon Laboratories Inc.
- Current Assignee Address: US TX Austin
- Agency: Nields, Lemack & Frame, LLC
- Main IPC: G01R31/3177
- IPC: G01R31/3177 ; G01R31/317 ; G06F21/74 ; G01R31/327

Abstract:
An integrated circuit having a secure domain is disclosed. Circuitry within the integrated circuit is used to select one of a plurality of scan modes. The sequence used to select one of the scan modes also serves to reset all of the flip-flops in the secure domain. In this way, it is impossible for a hacker to use the test modes to shift data from the secure domain out of the integrated circuit. The reset is generated asynchronously upon assertion of a first signal and is terminated upon the assertion of a second signal. The assertion of the second signal also serves to select one of the scan modes. This system cannot be hacked by any method that enters scan mode since it is a hardware based solution.
Public/Granted literature
- US20210263098A1 SECURE SCAN ENTRY Public/Granted day:2021-08-26
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