A controller of a memory system controls a completion rate of commands. The controller receives, from a host, command requests to be processed on a memory device. The controller processes the command requests, determines a first number of completion notifications, which are to be transmitted to the host in a first time interval, among multiple completion notifications associated with the command requests, based on a throughput credit, a set maximum credit, and the number of the multiple completion notifications. The controller transmits, to the host, the first number of completion notifications in the first time interval, and transmits a second number of completion notifications in the second time interval.