A memory device, of an electronic device, that controls a start of an operation of a sub microcontroller includes a plurality of memory cells. The memory device includes a command interface logic encoding a command received from an outside of the memory device to generate an encoding signal, a multi-microcontroller circuit including a main microcontroller and a sub microcontroller outputting a setting signal for performing an operation on the plurality of memory cells based on the encoding signal, and a read only memory outputting ROM data corresponding to a ROM address output from the multi-microcontroller circuit. The sub microcontroller receives a micro out signal output from the main microcontroller and simultaneously operates with the main microcontroller, during an operation of the main microcontroller.