In this paper, binary stackers and counters are presented. In an embodiment, a counter uses 3-bit stacking circuits which group T bits together, followed a symmetric method to combine pairs of 3-bit stacks into 6-bit stacks. The bit stacks are then converted to binary counts, producing 6:3 and 7:3 Counter circuits with no XOR gates on the critical path. This avoids of XOR gates results in faster designs with efficient power and area utilization. In VLSI simulations, the presently-disclosed counters were 30% faster and at consumed at least 20% less power than existing parallel counters. Additionally, using the presently-disclosed counter in existing Counter Based Wallace tree multiplier architectures reduce latency and improves efficiency in term of power-delay product for 64-bit and 128-bit multipliers.