A processing unit for a multiprocessor data processing system includes a processor core having an upper level cache and a lower level cache coupled to the processor core. The processor core is configured to, based on receipt of an interrupt, generate and issue a synchronization request prior to executing an interrupt handler and is configured to, based on receipt of a synchronization acknowledgment for the synchronization request, execute the interrupt handler. The lower level cache is configured to, based on receipt of the synchronization request, record which of its state machines are active processing a prior snooped request that can invalidate a cache line in the upper level cache, and is configured to, based on determining that each such state machine has completed processing of its respective prior snooped request, issue the synchronization acknowledgment to the processor core.