An interrupt rate limiter limits the rate of interrupt signals being transmitted from a first node to a second node of a computer system. In certain implementations, a first logic block compares an accumulator value to a threshold value to determine whether to (i) block an interrupt signal received from the first node from reaching the second node or (ii) allow the interrupt signal to reach the second node, an accumulator register stores the accumulator value, which is (i) increased whenever the first logic block allows an interrupt signal to reach the second node and (ii) otherwise periodically decreased, a summation node receives the accumulator value and one or more values that determine whether the accumulator value is to be increased or decreased, and a second logic block determines whether to increase or decrease the accumulator value based on whether an interrupt signal has been transmitted to the second processor.