Invention Grant
- Patent Title: Flattening portal bridge
-
Application No.: US17136347Application Date: 2020-12-29
-
Publication No.: US11321264B2Publication Date: 2022-05-03
- Inventor: David J. Harriman , Reuven Rozic , Maxim Dan , Prashant Sethi , Robert E. Gough , Shanthanand Kutuva Rabindranath
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Spectrum IP Law Group LLC
- Main IPC: G06F13/40
- IPC: G06F13/40 ; G06F13/42

Abstract:
A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.
Public/Granted literature
- US20210232522A1 FLATTENING PORTAL BRIDGE Public/Granted day:2021-07-29
Information query