A gate driver of array (GOA) circuit includes a plurality of cascaded GOA units, wherein an N-th GOA unit includes a scan control circuit, a reverse circuit, a gate signal output circuit, and a potential holding circuit. The reverse circuit is coupled to the scan control circuit. The gate signal output circuit is coupled to an Nth clock signal, the scan control circuit, and the reverse circuit. The potential holding circuit is coupled to the scan control circuit, the reverse circuit, and the gate signal output circuit.