Invention Grant
- Patent Title: Apparatuses and methods for calculating row hammer refresh addresses in a semiconductor device
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Application No.: US16805197Application Date: 2020-02-28
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Publication No.: US11322192B2Publication Date: 2022-05-03
- Inventor: Masaru Morohashi , Hidekazu Noguchi
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: G06F13/00
- IPC: G06F13/00 ; G11C11/406 ; G11C15/04 ; G11C8/10 ; G06F13/16 ; G11C16/34
Abstract:
An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.
Information query
