A power gating control circuit includes an operational period signal generating circuit, a period termination detecting circuit, a power gating period signal generating circuit and a power gating control signal generating circuit. The operational period signal generating circuit generates a plurality of operational period signals based on internal clock signals and one or more of command shift signals. The period termination detecting circuit generates a write period termination signal and a read period termination signal based on the command signals and the plurality of operational period signals. The power gating period signal generating circuit generates a first power gating period signal and a second power gating period signal based on the write period termination signal, the read period termination signal and remaining command shift signals other than the one or more command shift signals. The power gating control signal generating circuit generates a plurality of power gating control signals based on the first power gating period signal, the second power gating period signal, and other signals to control entry into and exit from a power-down mode of a semiconductor apparatus.