Invention Grant
- Patent Title: Interconnect structure without barrier layer on bottom surface of via
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Application No.: US16593562Application Date: 2019-10-04
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Publication No.: US11322391B2Publication Date: 2022-05-03
- Inventor: Tz-Jun Kuo , Chien-Hsin Ho , Ming-Han Lee
- Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing, Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing, Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/768 ; H01L23/522 ; H01L23/532

Abstract:
Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.
Public/Granted literature
- US20200035546A1 INTERCONNECT STRUCTURE WITHOUT BARRIER LAYER ON BOTTOM SURFACE OF VIA Public/Granted day:2020-01-30
Information query
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