Invention Grant
- Patent Title: Semiconductor device and semiconductor module with a highest portion of a terminal lower than a highest portion of the mold sealing resin
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Application No.: US16623402Application Date: 2018-01-23
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Publication No.: US11322430B2Publication Date: 2022-05-03
- Inventor: Hodaka Rokubuichi , Kuniyuki Sato , Kiyofumi Kitai , Yasuyuki Sanda
- Applicant: Mitsubishi Electric Corporation
- Applicant Address: JP Tokyo
- Assignee: Mitsubishi Electric Corporation
- Current Assignee: Mitsubishi Electric Corporation
- Current Assignee Address: JP Tokyo
- Agency: Xsensus LLP
- Priority: JPJP2017-146182 20170728
- International Application: PCT/JP2018/001939 WO 20180123
- International Announcement: WO2019/021507 WO 20190131
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L21/56 ; H01L23/31

Abstract:
A semiconductor device and a semiconductor module which can be reduced in size while ensuing insulation are provided. In the semiconductor device, a lead frame on which a circuit pattern is formed is provided on an insulation substrate; the circuit pattern of the lead frame is joined to the back-side electrode of a semiconductor chip via a solder layer, and the lead frame is electrically connected with the top-side electrode of the semiconductor chip via a wire; the lead frame 1 includes a terminal inside a mold-sealing resin and a terminal exposed to a space outside the mold-sealing resin, and the terminal is connected to a terminal block via a solder layer; and the lead frame, the insulation substrate, the semiconductor chip and the terminal block are integrally molded and sealed by the mold-sealing resin.
Public/Granted literature
- US20200176361A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE Public/Granted day:2020-06-04
Information query
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