Invention Grant
- Patent Title: Array substrate with first gate, second gate, binding region with hole, and manufacturing method of same
-
Application No.: US16641660Application Date: 2019-11-18
-
Publication No.: US11322569B2Publication Date: 2022-05-03
- Inventor: Cheng Chen , Yun Yu
- Applicant: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
- Applicant Address: CN Wuhan
- Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
- Current Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
- Current Assignee Address: CN Wuhan
- Priority: CN201910822395.6 20190902
- International Application: PCT/CN2019/119292 WO 20191118
- International Announcement: WO2021/042574 WO 20210311
- Main IPC: H01L27/32
- IPC: H01L27/32 ; H01L51/56

Abstract:
The present application provides an array substrate and a manufacturing method of the same, the array substrate includes a display region, the display region includes a thin film transistor structure layer including a gate electrode layer and a source drain electrode layer, wherein the gate electrode layer and the source drain electrode layer are made of an alloy material including one or a group selected from Al, Ge, Nd, Ta, Zr, Ni, or La.
Public/Granted literature
- US20210280660A1 ARRAY SUBSTRATE AND MANUFACTURING METHOD OF SAME Public/Granted day:2021-09-09
Information query
IPC分类: