Invention Grant
- Patent Title: SOI wafers and devices with buried stressor
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Application No.: US17089429Application Date: 2020-11-04
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Publication No.: US11322615B2Publication Date: 2022-05-03
- Inventor: Paul A. Clifton , Andreas Goebel
- Applicant: Acorn Semi, LLC
- Applicant Address: US CA Palo Alto
- Assignee: Acorn Semi, LLC
- Current Assignee: Acorn Semi, LLC
- Current Assignee Address: US CA Palo Alto
- Agency: Ascenda Law Group, PC
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/06 ; H01L27/12 ; H01L21/762 ; H01L21/02 ; H01L29/10

Abstract:
A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer.
Public/Granted literature
- US20210050450A1 SOI WAFERS AND DEVICES WITH BURIED STRESSOR Public/Granted day:2021-02-18
Information query
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