Invention Grant
- Patent Title: Multi-level drive data transmission circuit and method
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Application No.: US17055082Application Date: 2019-11-22
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Publication No.: US11323116B2Publication Date: 2022-05-03
- Inventor: Kangling Ji
- Applicant: ChangXin Memory Technologies, Inc.
- Applicant Address: CN Hefei
- Assignee: ChangXin Memory Technologies, Inc.
- Current Assignee: ChangXin Memory Technologies, Inc.
- Current Assignee Address: CN Hefei
- Agency: Alston & Bird LLP
- Priority: CN201910786276.X 20190823
- International Application: PCT/CN2019/120279 WO 20191122
- International Announcement: WO2021/036034 WO 20210304
- Main IPC: G06F9/38
- IPC: G06F9/38 ; H03K19/094 ; G11C7/10 ; G11C7/22 ; H03K3/0233 ; H03K19/20

Abstract:
The disclosed multi-level driving data transmission circuit and operating method include: a first driving module including a first signal generating unit and a first three-state driver, and a second driving module, including a second three-state driver. The first input terminal of the second three-state driver is coupled to the output terminal of the first three-state driver. The first signal generating unit includes a first and second input terminals, and an output terminal. The output terminal of the first signal generating unit couples to the second input terminal of the first three-state driver. The first signal generating unit receives the first signal through its first input terminal and the first feedback signal of the first signal from the second driving module through its second input terminal. The resultant first control signal has an effective signal width wider than the first signal. The first control signal inputs to the first three-state driver.
Public/Granted literature
- US20210367601A1 MULTI-LEVEL DRIVE DATA TRANSMISSION CIRCUIT AND METHOD Public/Granted day:2021-11-25
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