- Patent Title: Low latency video codec and transmission with parallel processing
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Application No.: US17129424Application Date: 2020-12-21
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Publication No.: US11323729B2Publication Date: 2022-05-03
- Inventor: Michael W. Bruns , Martin A. Hunt , Manjunath H. Siddaiah , John C. Sievers
- Applicant: Coherent Logix, Incorporated
- Applicant Address: US TX Austin
- Assignee: Coherent Logix, Incorporated
- Current Assignee: Coherent Logix, Incorporated
- Current Assignee Address: US TX Austin
- Agency: Kowert, Hood, Munyon, Rankin & Goetzel, P.C.
- Main IPC: H04N19/436
- IPC: H04N19/436 ; G06F9/38 ; H04N19/176 ; H04N19/146 ; H04N19/107 ; H04N19/147

Abstract:
Methods and devices are described for a parallel multi-processor encoder system for encoding video data, wherein the video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system may divide the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks may be transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.
Public/Granted literature
- US20210152839A1 Low Latency Video Codec and Transmission with Parallel Processing Public/Granted day:2021-05-20
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