Invention Grant
- Patent Title: Capacitive compensation for vertical interconnect accesses
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Application No.: US17078471Application Date: 2020-10-23
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Publication No.: US11324119B1Publication Date: 2022-05-03
- Inventor: Hansel Desmond Dsilva , Sasikala J , Abhishek Jain , Amit Kumar
- Applicant: Achronix Semiconductor Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Achronix Semiconductor Corporation
- Current Assignee: Achronix Semiconductor Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H05K3/40
- IPC: H05K3/40 ; H05K1/11 ; H05K1/02 ; G01R27/16 ; H05K3/46 ; H05K3/04 ; H05K3/00 ; H05K3/42

Abstract:
Multiple designs for a multi-layer circuit may be simulated to determine impedance profiles of each design, allowing a circuit designer to select a design based on the impedance profiles. One feature that can be modified is the structure surrounding the barrels of a differential VIA on layers that are not connected to the differential VIA. Specifically, one antipad can be used that surrounds both barrels or two antipads can be used, with one antipad for each barrel. Additionally, the size of the antipad or antipads can be modified. These modifications affect the impedance of the differential VIA. Additionally, a conductive region may be placed that connects to the VIA barrel even though the circuit on the layer does not connect to the VIA. This unused pad, surrounded by a non-conductive region, also affects the impedance of the differential VIA.
Public/Granted literature
- US20220132663A1 Capacitive Compensation for Vertical Interconnect Accesses Public/Granted day:2022-04-28
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