- Patent Title: Double-side polishing method and double-side polishing apparatus
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Application No.: US16061841Application Date: 2017-02-01
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Publication No.: US11325220B2Publication Date: 2022-05-10
- Inventor: Yuki Tanaka , Shiro Amagai
- Applicant: SHIN-ETSU HANDOTAI CO., LTD.
- Applicant Address: JP Tokyo
- Assignee: SHIN-ETSU HANDOTAI CO., LTD.
- Current Assignee: SHIN-ETSU HANDOTAI CO., LTD.
- Current Assignee Address: JP Tokyo
- Agency: Oliff PLC
- Priority: JPJP2016-027136 20160216
- International Application: PCT/JP2017/003568 WO 20170201
- International Announcement: WO2017/141704 WO 20170824
- Main IPC: B24B37/08
- IPC: B24B37/08 ; B24B37/04 ; B24B37/24 ; B24B37/28 ; H01L21/00 ; H01L21/02 ; H01L21/67

Abstract:
A double-side polishing method, including: simultaneously polishing both surfaces of a semiconductor wafer by holding the semiconductor wafer in a carrier, interposing the held semiconductor wafer between an upper turn table and a lower turn table each having a polishing pad attached thereto, and bringing both surfaces of the semiconductor wafer into sliding contact with the polishing pads, wherein the semiconductor wafer is polished under a condition that a thickness A (mm) of the polishing pad attached to the upper turn table and a thickness B (mm) of the polishing pad attached to the lower turn table satisfy relations of 1.0≤A+B≤2.0 and A/B>1.0. This provides a double-side polishing method capable of obtaining a semiconductor wafer in which F-ZDD
Public/Granted literature
- US20180361530A1 DOUBLE-SIDE POLISHING METHOD AND DOUBLE-SIDE POLISHING APPARATUS Public/Granted day:2018-12-20
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