Invention Grant
- Patent Title: Method and apparatus for eliminating bit disturbance errors in non-volatile memory devices
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Application No.: US16782139Application Date: 2020-02-05
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Publication No.: US11327882B2Publication Date: 2022-05-10
- Inventor: Muhammed Sarwar , Vyankatesh Gupta , James McClay , Sundar Chetlur , Harianto Wong , Gerardo A. Monreal , Nicolás Rafael Biberidis , Octavio H. Alpago , Nicolas Rigoni
- Applicant: Allegro MicroSystems, LLC
- Applicant Address: US NH Manchester
- Assignee: Allegro MicroSystems, LLC
- Current Assignee: Allegro MicroSystems, LLC
- Current Assignee Address: US NH Manchester
- Agency: Daly, Crowley, Mofford & Durkee, LLP
- Main IPC: G06F12/02
- IPC: G06F12/02 ; G06F9/30 ; G11C16/26

Abstract:
A method comprising: performing a first read from an address in a data storage module by using a first read voltage; storing, in a first register, data that is retrieved from the data storage module as a result of the first read; performing a second read from the address by using a second read voltage; storing, in a second register, data that is retrieved from the data storage module as a result of the second read; detecting whether a weak bit condition is present at the address based on the data that is stored in the first register and the data that is stored in the second register; and correcting the weak bit condition, when the weak bit condition is present at the address.
Public/Granted literature
- US20210240606A1 METHOD AND APPARATUS FOR ELIMINATING BIT DISTURBANCE ERRORS IN NON-VOLATILE MEMORY DEVICES Public/Granted day:2021-08-05
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