A semiconductor memory apparatus includes a memory cell array, a peripheral circuit, and control logic. The memory cell array may include a plurality of memory cells. The peripheral circuit performs a program operation on selected memory cells among the plurality of memory cells. The control logic controls an operation of the peripheral circuit. The control logic controls the peripheral circuit to perform a pre-program operation on first memory cells to be programmed to an upper programmed state among the selected memory cells and perform a normal program operation on the selected memory cells after the pre-program operation.